The invention relates to an arrangement comprising a connection module for boundary scan testing ("BST") of a carrier on which digital ICs are arranged. A number of ICs are provided with BST test logic and a number of ICs are not provided with BST test logic.
The BST method is described in "Boundary-Scan Test, A. Practical Approach", Harry Bleeker, Peter van den Eijnden and Frans de Jong, Kluwer, Boston, 1993, ISBN 0-7923-9296-5. Pages 157 to 166 describe the testing of carriers, on which a number of ICs are provided with BST test logic.
Contemporary carriers often comprise a number of ICs with BST test logic and a number of ICs without BST test logic. The interconnections or interconnections to the latter ICs can be tested by controlling these ICs from neighbouring ICs that are provided with BST logic.
The interconnection function is for example to be understood as:
a. the conductor pattern provided on the carrier; PA0 b. the connection between this pattern and the pins of the ICs; PA0 c. the connection between these pins and the bond pads provided on the substrate of the IC.
It is a drawback that this method of controlling and testing the ICs by means of the neighbouring ICs is comparatively slow. This is due to the fact that the test signals reach the non-BST ICs to be tested via a chain of registers. Slow testing has as a consequence that, for example in the case of DRAMs, the interval between two consecutive cycles is too long.